1. Field of the Invention
The present disclosure relates to programming in non-volatile memory.
2. Description of the Related Art
Semiconductor memory devices have become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM), including flash EEPROM, and Electronically Programmable Read Only Memory (EPROM) are among the most popular non-volatile semiconductor memories.
EEPROM and EPROM memories utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. The minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
One example of a flash memory system uses the NAND structure, which includes arranging multiple transistors in series between two select gates. The transistors in series and the select gates are referred to as a NAND string. FIG. 1 is a top view showing one NAND string and FIG. 2 is an equivalent circuit thereof. The NAND string depicted in FIGS. 1 and 2 includes four transistors 100, 102, 104 and 106 in series between a first select gate 120 and a second select gate 122. The drain select gate 120 connects the NAND string to bit line 126. The source gate 122 connects the NAND string to source line 128. Select gate 120 is controlled by applying appropriate voltages to control gate 120CG via selection line SGD. Select gate 122 is controlled by applying the appropriate voltages to control gate 122CG via selection line SGS. Each of the transistors 100, 102, 104 and 106 includes a control gate and a floating gate, forming the gate elements of a memory cell. Transistor 100 includes control gate 100CG and floating gate 100FG. Transistor 102 includes control gate 102CG and a floating gate 102FG. Transistor 104 includes control gate 104CG and floating gate 104FG. Transistor 106 includes a control gate 106CG and a floating gate 106FG. Control gate 100CG is connected to word line WL3, control gate 102CG is connected to word line WL2, control gate 104CG is connected to word line WL1, and control gate 106CG is connected to word line WL0. Another type of memory cell useful in flash EEPROM systems utilizes a non-conductive dielectric material in place of a conductive floating gate to store charge in a non-volatile manner.
Note that although FIGS. 1 and 2 show four memory cells in the NAND string, the use of four transistors is only provided as an example. A NAND string can have less than four memory cells or more than four memory cells. For example, some NAND strings will include eight memory cells, 16 memory cells, 32 memory cells, etc. The discussion herein is not limited to any particular number of memory cells in a NAND string and any described embodiments can be suitably incorporated into systems with any number of cells per string. Relevant examples of NAND-type flash memories and their operation are provided in the following U.S. patents/patent applications, all of which are incorporated herein by reference in their entirety: U.S. Pat. Nos. 5,570,315; 5,774,397; 6,046,935; 5,386,422; 6,456,528; and U.S. patent application Ser. No. 09/893,277 (Publication No. US2003/0002348).
A typical architecture for a flash memory system using a NAND structure will include several NAND strings. For example, FIG. 3 shows three NAND strings of a memory array having many more NAND strings. Each NAND string includes two select transistors or gates and four memory cells in FIG. 3. NAND string 190 includes select transistors 150 and 180, and memory cells 152, 154, 156 and 158. NAND string 192 includes select transistors 160 and 182, and memory cells 162, 164, 166 and 168. NAND string 194 includes select transistors 170 and 184, and memory cells 172, 174, 176, and 178. Each string is connected to the source line by one of source select gates 180, 182 and 184. Selection line SGS is used to control the source side select gates. The NAND strings are connected to respective bit lines by drain select gates 150, 160 and 170, which are controlled by selection line SGD. In other embodiments, the select lines do not necessarily need to be in common. Word line WL3 is connected to the control gates for memory cells 152, 162 and 172. Word line WL2 is connected to the control gates for memory cells 154, 164, and 174. Word line WL1 is connected to the control gates for memory cells 156, 166 and 176. Word line WL0 is connected to the control gates for memory cells 158, 168 and 178. A bit line and respective NAND string comprise a column of the array of memory cells. The word lines comprise the rows of the array. Each word line connects the control gates of each memory cell in the row. In some implementations, the word lines form the control gates of each memory cell in the row, while in others the word lines are formed separately and then connected to the control gates for a row of memory cells.
One programming methodology for EEPROM or flash memory devices uses Fowler Nordheim (FN) tunneling. IN FN programming a program voltage is typically applied to the control gate of a memory cell while the corresponding bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised so that the memory cell is in a programmed state. The floating gate charge and threshold voltage of the cell can be indicative of a particular state corresponding to stored data (analog or digital). More information about programming can be found in U.S. patent application Ser. No. 10/629,068, titled “Detecting Over Programmed Memory,” filed on Jul. 29, 2003, incorporated herein by reference in its entirety.
A program voltage is applied on the appropriate word line to apply the program voltage to the control gate of the cell being programmed. As discussed above, that word line is also connected to one cell in each of the other NAND strings that utilize the same word line. For example, when programming cell 154 of FIG. 3, the program voltage will also be applied to the control gate of cells 164 and 174 because both cells share the same word line WL2. A problem arises when it's desired to program one cell on a word line without programming other cells connected to the same word line. Because the program voltage is applied to all cells connected to a word line, an unselected cell connected to the selected word line receiving the program voltage, especially a cell adjacent to the cell selected for programming, may be inadvertently programmed. The unintentional programming of the unselected cell on the selected word line is referred to as “program disturb.”
Several techniques can be employed to prevent program disturb. In one method known as “self boosting,” the channel areas of the unselected NAND strings are electrically isolated and a pass voltage (e.g. 10V) is applied to the unselected word lines during programming. The unselected word lines couple to the channel areas of the unselected NAND strings, causing a voltage (e.g. 8V) to be impressed in the channel and source/drain regions of the unselected NAND strings, thereby reducing program disturb. Self boosting causes a voltage boost to exist in the channel which lowers the voltage across the tunnel oxide and hence reduces program disturb.
Another programming methodology used in flash memory is source-side injection programming (SSI), which can offer some improvements over Fowler-Nordheim based programming. Lower programming currents and improvements in program disturb may be possible with SSI programming. In source-side injection (SSI) programming, a high voltage drain region at an injector gate excites hot electrons which are injected near the source side of a selected memory cell. A programming current from drain to source through the selected memory cell (e.g., memory cell 104) is induced by a high voltage drain region. The injector gate (e.g., memory cell 106) is turned on, causing a high electric field at its drain region. The drain region of the injector gate is near the source region of the selected memory cell, causing electrons to accumulate at the source side of the selected memory cell through hot electron injection. Although SSI programming offers some improvements over FN programming, its use in an array of memory cells can present difficulties.